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NXP Semiconductors /LPC176x5x /SSP1 /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NORMAL)LBM 0 (DISABLED)SSE 0 (MASTER)MS 0 (SOD)SOD 0RESERVED

SSE=DISABLED, LBM=NORMAL, MS=MASTER

Description

Control Register 1. Selects master/slave and other modes.

Fields

LBM

Loop Back Mode.

0 (NORMAL): During normal operation.

1 (OUPTU): Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
SSE

SSP Enable.

0 (DISABLED): The SSP controller is disabled.

1 (ENABLED): The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.
MS

Master/Slave Mode.This bit can only be written when the SSE bit is 0.

0 (MASTER): The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.

1 (SLAVE): The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.
SOD

Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data